Goldmont

Goldmont
Model	Atom
Transistors	14 nm transistors
Architecture	Goldmont x86
Instructions	MMX, AES-NI, CLMUL
Extensions	x86-64, Intel 64 SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2 VT-x
Predecessor	Airmont (die shrink)

Goldmont is a microarchitecture for low-power Atom, Celeron and Pentium branded processors used in systems on a chip (SoCs) made by Intel. The Apollo Lake platform with 14 nm Goldmont core was unveiled at the Intel Developer Forum (IDF) in Shenzen, China, April 2016.^[1] The Goldmont architecture borrows heavily from the Skylake Core processors, so offers more than 30 percent performance boost compare to the previous Braswell platform, and it can be used to implement power-efficient low-end devices including Cloudbooks, 2-in-1 netbooks, small PCs, IP cameras, and in-car entertainment systems.^[2]^[3]

Design

Goldmont is the 2nd generation out-of-order low-power Atom microarchitecture designed for the entry level desktop and notebook computers.^[4] Goldmont is built on the 14 nm manufacturing process and supports up to four cores for the consumer devices. It includes the Intel Gen9 graphics architecture introduced with the Skylake.

The Goldmont microarchitecture builds on the success of the Silvermont microarchitecture, and provides the following enhancements:

An out-of-order execution engine with a 3-wide superscalar pipeline. Specifically:
- The decoder can decode 3 instructions per cycle.
- The microcode sequencer can send 3 µops per cycle for allocation into the reservation stations.
- Retirement supports a peak rate of 3 per cycle.
Enhancement in branch prediction which de-couples the fetch pipeline from the instruction decoder.
Larger out-of-order execution window and buffers that enable deeper out-of-order execution across integer, FP/SIMD, and memory instruction types.
Fully out-of-order memory execution and disambiguation. The Goldmont microarchitecture can execute one load and one store per cycle (compared to one load or one store per cycle in the Silvermont microarchitecture). The memory execution pipeline also includes a second level TLB enhancement with 512 entries for 4KB pages.
Integer execution cluster in the Goldmont microarchitecture provides three pipelines and can execute up to three simple integer ALU operations per cycle.
SIMD integer and floating-point instructions execute in a 128-bit wide engine. Throughput and latency of many instructions have improved, including PSHUFB with 1-cycle throughput (versus 5 cycles for Silvermont microarchitecture) and many other SIMD instructions with doubled throughput.
Throughput and latency of instructions for accelerating encryption/description (AES) and carry-less multiplication (PCLMULQDQ) have been improved significantly in the Goldmont microarchitecture.
The Goldmont microarchitecture provides new instructions with hardware accelerated secure hashing algorithm, SHA1 and SHA256.
The Goldmont microarchitecture also adds support for the RDSEED instruction for random number generation meeting the NIST SP800-90C standard.
PAUSE instruction latency is optimized to enable better power efficiency.

Technology

List of Goldmont processors

Desktop processors (Apollo Lake)

List of desktop processors as follows:^[3]^[5]

Target segment	Cores (Threads)	Processor Branding & Model		GPU Model		TDP	CPU Clock rate		Graphics Clock rate		L2 Cache	Release Date	Price (USD)
Target segment	Cores (Threads)	Processor Branding & Model		GPU Model		TDP	Base	Turbo	Normal	Turbo	L2 Cache	Release Date	Price (USD)
Desktop	4 (4)	Pentium	J4205	Intel HD Graphics 505	(18 EU)	10 W	1.5 GHz	2.6 GHz	250 MHz	800 MHz	2 MB	Q3 2016	$161
	4 (4)	Celeron	J3455	Intel HD Graphics 500	(12 EU)		1.5 GHz	2.3 GHz		750 MHz			$107
	2 (2)	Celeron	J3355	Intel HD Graphics 500	(12 EU)		2.0 GHz	2.5 GHz		700 MHz			$107

Mobile processors (Apollo Lake)

List of mobile processors as follows:^[3]^[5]

Target segment	Cores (Threads)	Processor Branding & Model		GPU Model		TDP	CPU Clock rate		Graphics Clock rate		L2 Cache	Release Date	Price (USD)
Target segment	Cores (Threads)	Processor Branding & Model		GPU Model		TDP	Base	Turbo	Normal	Turbo	L2 Cache	Release Date	Price (USD)
Mobile	4 (4)	Pentium	N4200	Intel HD Graphics 505	(18 EU)	6 W	1.1 GHz	2.5 GHz	200 MHz	750 MHz	2 MB	Q3 2016	$161
	4 (4)	Celeron	N3450	Intel HD Graphics 500	(12 EU)			2.2 GHz		700 MHz			$107
	2 (2)	Celeron	N3350	Intel HD Graphics 500	(12 EU)			2.4 GHz		650 MHz			$107

References

↑ Eric Brown (2016-04-18). ""Apollo Lake" Atoms to offer graphics-rich Goldmont cores". Hackerboards.com. Retrieved 2016-06-11.
↑ Anton Shilov (2016-04-15). "Intel Unveils New Low-Cost PC Platform: Apollo Lake with 14nm Goldmont Cores". Anandtech.com. Retrieved 2016-06-11.
1 2 3 Alexander Fagot/ Allen Ngo (2016-06-07). "Intel claims Apollo Lake will be 30 percent faster than Braswell". Notebookcheck.net. Retrieved 2016-06-11.
↑ Anton Shilov (2015-06-10). "Intel preps 'Apollo Lake' CPUs with 'Goldmont' cores, Gen9 graphics". Retrieved 2016-06-11.
1 2 Gennadiy Shvets (2016-06-09). "Model numbers of Apollo Lake processors revealed". cpu-world.com. Retrieved 2016-06-11.

Intel processors

Discontinued

BCD oriented (4-bit)	4004 (1971) 4040 (1974)

pre-x86 (8-bit)	8008 (1972) 8080 (1974) 8085 (1977)

Early x86 (16-bit)	8086 (1978) 8088 (1979) 80186 (1982) 80188 (1982) 80286 (1982)

x87 (external FPUs)	8/16-bit databus 8087 (1980) 16-bit databus 80187 80287 80387SX 32-bit databus 80387DX 80487

IA-32 (32-bit)	80386 SX 376 EX 80486 SX DX2 DX4 SL RapidCAD OverDrive A100/A110 Celeron (1998) M D (2004) Pentium Original OverDrive Pro II II OverDrive III 4 M Dual-Core Core Solo Duo

x86-64 (64-bit)	Celeron D Dual-Core Pentium 4 D Extreme Edition Dual-Core Core 2 i7 (some)

Other	CISC iAPX 432 RISC i860 i960 StrongARM XScale

Current

IA-32 (32-bit)	Tolapai Atom CE SoC Quark

x86-64 (64-bit)	Atom CE SoC Celeron Pentium Core i3 i5 i7 M Xeon E7 E5 E3 Phi

EPIC	Itanium

Lists

Atom Celeron Core 2 i3 i5 i7 M Itanium Pentium Pro II III 4 D M Xeon

Related

Chipsets PCHs SCHs ICHs PIIXs GPUs Codenames GMA HD and Iris Graphics

Microarchitectures

P5	800 nm P5 600 nm P54C 350 nm P54CS P55C 250 nm Tillamook

P6 / Pentium M / Enhanced Pentium M	500 nm P6 350 nm P6 Klamath 250 nm Mendocino Dixon Tonga Covington Deschutes Katmai Drake Tanner 180 nm Coppermine Coppermine T Timna Cascades 130 nm Tualatin Banias 90 nm Dothan Stealey Tolapai Canmore 65 nm Yonah Sossaman

NetBurst	180 nm Willamette Foster 130 nm Northwood Gallatin Prestonia 90 nm Tejas and Jayhawk Prescott Smithfield Nocona Irwindale Cranford Potomac Paxville 65 nm Cedar Mill Presler Dempsey Tulsa

Core / Penryn	65 nm Merom-L Merom Conroe-L Allendale Conroe Kentsfield Woodcrest Clovertown Tigerton 45 nm Penryn Penryn-QC Wolfdale Yorkfield Wolfdale-DP Harpertown Dunnington

Bonnell / Saltwell	45 nm Silverthorne Diamondville Pineview Lincroft Tunnel Creek Stellarton Sodaville Groveland 32 nm Cedarview Penwell Cloverview Berryville Centerton

Nehalem / Westmere	45 nm Clarksfield Lynnfield Jasper Forest Bloomfield Gainestown (Nehalem-EP) Beckton (Nehalem-EX) 32 nm Arrandale Clarkdale Gulftown (Westmere-EP) Westmere-EX

Sandy Bridge / Ivy Bridge	32 nm Sandy Bridge Sandy Bridge-E Gladden 22 nm Ivy Bridge Ivy Bridge-EP Ivy Bridge-EX

Haswell / Broadwell	22 nm Haswell 14 nm Broadwell

Silvermont / Airmont	22 nm Valleyview Tangier Anniedale 14 nm Cherryview

Skylake/Kaby Lake/Coffee Lake/Cannonlake	14 nm Skylake Kaby Lake Coffee Lake 10 nm Cannonlake

Goldmont	14 nm Goldmont

Future (Icelake/Tigerlake)	10 nm Icelake Tigerlake

Intel CPU core roadmaps from NetBurst and P6 to Tigerlake

Atom (ULV)		Feature size	x86
		600 nm	P6	Pentium Pro (133 MHz)
		500 nm		Pentium Pro (150 MHz)
		350 nm		Pentium Pro (166–200 MHz)
				Klamath
		250 nm		Deschutes
				Katmai		NetBurst
		180 nm		Coppermine		Willamette
		130 nm		Tualatin		Northwood
				Banias				NetBurst(HT)		NetBurst(×2)
		90 nm		Dothan		Prescott	⇨	Prescott‑2M	⇨	Smithfield
						Tejas	→	⇩	→	Cedarmill (Tejas)
		65 nm		Yonah		Nehalem (NetBurst)		Cedar Mill	⇨	Presler
			Core	Merom
Bonnell	Bonnell	45 nm		Penryn
			Nehalem	Nehalem
	Saltwell	32 nm		Westmere
			Sandy Bridge	Sandy Bridge
Silvermont	Silvermont	22 nm		Ivy Bridge
			Haswell	Haswell
	Airmont	14 nm		Broadwell
Goldmont	Goldmont		Skylake	Skylake
				Kaby Lake	⇨	Coffee Lake
		10 nm		Cannonlake
			Icelake	Icelake
				Tigerlake

Italic names indicate canceled processors
Bold names are the microarchitecture names
Bold italic names are future processors

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