Cannonlake

This article is about Intel CPU microarchitecture. For other uses, see Cannon Lake.
Cannonlake
Created H2 2017[1]
Transistors 10 nm transistors
Architecture x86
Instructions MMX, AES-NI, CLMUL, FMA3
Extensions
Socket LGA 1151{[3]}
Predecessor
Successor
Brand name(s)
    • Core M
    • Core i3
    • Core i5
    • Core i7
    • Celeron
    • Pentium
    • Xeon

Cannonlake (formerly Skymont) is Intel's codename for the 10-nanometer die shrink of the Kaby Lake microarchitecture, expected to be released in the second half of 2017.[1][6] As a die shrink, Cannonlake is a new process in Intel's "Process-Architecture-Optimization" execution plan as the next step in semiconductor fabrication.[7] Cannonlake will be used in conjunction with Intel 200 Series chipsets, also known as Union Point. The platform as a whole will be named Union Bay.[7]

It has been speculated for a long time that reaching smaller process nodes would become impractical, leading to the end of Moore's Law. Intel however believes that it will be possible to reach at least 7 nm, though it will perhaps require use of materials other than silicon,[8] such as indium gallium arsenide (InGaAs).

Due to low 10 nm yields, Cannonlake will be limited to 15 Watt U and 5.2 Watt Y system-on-chip parts with GT2. Higher power mobile and desktop platforms will receive an update in the form of a 2nd 14 nm process refinement, Coffee Lake, that is said to share Cannonlake's architectural refinements.

The successors of the Cannonlake microarchitecture will be Icelake (2018) and Tigerlake (2019), which will represent Architecture and Optimization of the Intel Process-Architecture-Optimization Model.[9][10]

Features

See also

References

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