SDS 9 Series

The SDS 9 Series computers are a backward compatible line of transistorized computers produced by Scientific Data Systems in the 1960s and 70s. This line includes the SDS 910, SDS 920, SDS 925, SDS 930, SDS 940, and the SDS 945. The SDS 9300 is an extension of the 9xx architecture. The SDS 92 is an incompatible 12-bit system built using monolithic integrated circuits.

The 910 and 920 were first shipped in August, 1962. The 9300 was announced in June, 1963.[1] The 925 and 930 were announced in 1964.[1] The 940 was announced in 1965,[2] and the 945 in 1968.[3]

General description

All systems are 24-bit single address machines. Programmer-accessible registers are A (accumulator), B (extension), X (index), and P (program counter—14 bits), plus an overflow indicator. The 9300 has three index registers X1 through X3 which can be used as base registers to allow access to memory above 16K words. The W and Y registers are used for input/output.

Maximum address space is 214 or 16,384 words (16K) on the 910 and 920; The 9300, 930, and 940 support up to 32K, although the method of accessing additional memory varies.

Data formats

Fixed point data is 24-bits, two's complement, big-endian.

Floating point is implemented in software using "programmed operators", except on the SDS 9300 which has hardware floating point. All floating point data is 48 bits, Single precision uses a 24-bit signed fraction and a 9-bit signed exponent, double precision uses a 39-bit fraction and a 9-bit exponent. Both the exponent and the fraction are stored in big-endian twos-complement format. The binary point is assumed to be immediately left of the high-order bit of the fraction. The value of the number is F*2E, where F is the fraction and E is the exponent.

The floating point formats are:

Double precision floating point
    +-+-----------------------+
    |±| Fraction              | high-order word
    +-+-----------+-+---------+
    | frac(cont)  |±|exponent | low-order word
    +-------------+-+---------+
bit  0             1         2
                   5         3
High-order word:
  bit   0    fraction sign
  bits  1-23 high-order part of fraction 
Low-order word:
  bits  0-14 low-order part of fraction 
  bit  15    exponent sign
  bits 16-23 exponent 

Single precision floating point
    +-+-----------------------+
    |±| Fraction              | high-order word
    +-+-----------+-+---------+
    | not used    |±|exponent | low-order word
    +-------------+-+---------+
bit  0             1         2
                   5         3
The format is the same as double precision except that only 24 bits of fraction are used.

Address generation

For address generation, indexing, if specified, is performed before indirection. The word at the effective indirect address is decoded as if it were an instruction (except that the instruction code is ignored), allowing an indirect address to also specify indirection or indexing. Multiple levels of indirect addressing are allowed.

Programmed operators

The programmed operator facility allows the instruction code field to indicate a call to a vector of subroutine addresses. The six bit instruction code allows up to 64 programmed operators (octal 00 through 77). If the P bit is set, an instruction code of xx is treated as a call to location 1xx (octal). The location of the POP instruction is saved in location zero. Bit zero of location zero is set to the current value of the overflow indicator and the indicator is reset. Bit 9 of location zero is set to '1'b to indicate an indirect address, allowing the programmed operator routine to indirectly access the data specified in the address of the POP instruction.

SDS 910

Main memory on the 910 is 2048 to 16384 words of magnetic-core memory with a cycle time of 8 μs. A fixed-point add instruction takes 16 μs, a fixed-point multiply takes 248 μs. Two hardware interrupts are standard with up to 896 more optional.

The instruction format for the 910 and 920 systems is as follows:

    +-+-+-+------+-+--------------+
    |0|X|P|Opcode|I|  Address     |
    +-+-+-+------+-+--------------+
bit  0 1 2 3    3 9 1            2
                    0            3
Bits 0-2 are called the "tag" 
Bit   0     is always zero.
Bit   1     '1'b indicates that this instruction is indexed.
Bit   2     '1'b indicates that this instruction 
            is a programmed operator (POP).
Bits  3-8   is the instruction code or programmer operator id.
Bit   8     '1'b indicates an indirect address.
Bits 10-23  Contain the operand address.

SDS 920

Main memory on the 920 is 4096 to 16384 words of magnetic core memory. The fixed-point add time is the same as the 910 (16 μs), but the fixed-point multiply is roughly twice as fast at 128 μs. The 920 can have up to 1024 priority interrupts.

SDS 930

Main article: SDS 930

The 930 offers a "memory extension system" that allows addressing more than 16284 words. Two 3-bit "Extend Memory Registers", called EM2 and EM3, are provided which can be loaded with a value to be used as the high-order three bits of the effective address. Addresses 000008–177778 (the first 8192 words of memory) are always unmodified. If the high-order octal digit of the address in the instruction is two the contents of EM2 replaces the high-order digit in the effective address; when the digit is three the contents of EM3 are used.

To retain compatibility with earlier models. when the computer is started the value in EM2 is set to 2 and EM3 to 3, allowing programs to address the first 16384 words of memory. These registers can be loaded by the program.

The program loader uses the high-order bit of the instruction, ignored by all models, as a flag indicating that the instruction currently being loaded is to be relocated.

930 memory has a cycle time of 1.75 μs. A fixed-point add takes 3.5 μs, and a fixed-point multiply 7.0 μs. The priority interrupt system allows 2–38 input/output interrupts and up to 896 system interrupts.

The instruction format for the 930 system is compatible with prior systems except for the bits used for extended memory:

    +-+-+-+------+-+--+----------+
    |0|X|P|Opcode|I|EM| Address  |
    +-+-+-+------+-+--+----------+
bit  0 1 2 3    3 9 11 1        2
                    01 2        3
Bits 10 and 11 specify either no extended memory
 (EM='00'b—references first 8K words of memory)
or prepend the contents of
 EM2 (EM='10'b) or
 EM3 (EM='11'b)
 to form the effective address.

SDS 940

Main article: SDS 940

The 940 adds modes of operation to support multiple users. The operating mode of previous models is renamed normal mode. A new monitor mode limits access to input/output and certain privileged instructions. A user mode is used to run users' application programs.

A set of memory map registers is used to map virtual addresses to physical. There are eight memory map registers, each mapping 2K words, to provide an address space of 16K.

The instruction format for normal mode is the same as for the 930. Addressing differs between user mode and monitor mode.[4]:p.6

SDS 940 user mode instruction format:
    +-+-+-+------+-+---+---------+
    |U|X|P|Opcode|I|Blk| Address |
    +-+-+-+------+-+---+---------+
bit  0 1 2 3    3 9 1   1       2
                    0   3       3
Bit 0 is ignored in user mode unless bit position 2 (P)
indicates that this is a programmed operator.  
In this case a '1'b in bit position 0 indicates that this is a "system POP", or "SYSPOP", instead of a standard programmed operator.

In user mode bit positions 10–12 "constitute a virtual memory block number", that is specify a memory map register, and bits 13–23 "specify a location within the virtual memory block."
The contents of the memory map register are prepended to instruction bits 13–23 to form the effective address.

Memory map

The 940 accesses memory through a memory map[note 1] to provide virtual memory. The map formats differ slightly between a user memory map and a monitor memory map.

For programs running in user mode, the high-order three bits of the address field of an instruction serve as an index to an array of eight registers (R0-R7).[note 2] Each register contains a 5-bit value (Rn) which is prepended to the low-order 11 bits of the instruction address field to form the 16-bit physical address. This divides virtual memory logically into eight blocks of 2048 words each. The registers allow access to 16K words at any one time out of a possible 32K words of physical memory. A sixth bit (Pn) in each register indicates a read-only block of storage. Rn=0 and Pn=1 indicates an unassigned block, and any reference causes a trap. The map registers can only be set in monitor mode.

The memory map for monitor mode is similar. There are no P bits; the R0–R5 equivalents, called M0–M5, contain the read-only values 0–5, providing direct access to physical addresses 0–8K-1 (00000–177778). For addresses in the range 8K–12K-1 (20000–277778) memory extension register EM2 is used to form the physical address as it is in in normal mode. For addresses 12K–16K-1 (30000–377778) the contents of memory map registers M6 and M7 are used to form the address.

The monitor can use either the monitor memory map or the user memory map, determined by the value of bit 0 of the instruction. This allows the monitor access to the user's address space.

System programmed operators

In user mode, programmed operators function the same as normal mode, accessing the user's virtual locations 100-1778. The 940 also includes a facility to execute System Programmed operators (SYSPOPS), used to call monitor services. When a SYSPOP is encountered in user mode (instruction bits 0 and 2 are '1'b), the computer first enters monitor mode and then accesses the vector of instructions at the monitor's (physical) 100-1778.

SDS 945

The 945 is an upgrade of the 940 time-sharing system. It was advertised as being able to "support up to 24 simultaneous users and up to 64 authorized users."[3]

Software

The primary operating system for the line, excluding the 940 and 945, is the MONARCH operating system. MONARCH is a single-task batch operating system. Originally resident on magnetic tape, later versions can reside on a head-per-track magnetic disk called a RAD (Rapid Access Data) File. MONARCH is not an executive system, since application programs have control of all the resources of the compute when running. Instead it is a monitor, providing job-to-job transition and supporting services to applications.

The monitor routine accepts control information which, among other things, may include a request to load and execute a specified standard system routine. The monitor performs its functions between jobs and does not exercise control over the execution of a program once that program has been loaded and the monitor has transferred control to it.
...
That portion of the monitor which remains in core memory during program execution consists of the Monitor Bootstrap Routine and the Unit Assignment Table.

Other standard system routines that are included in the monitor are:[5]

By 1969 an ALGOL 60 compiler was available.[6]

See also

Notes

  1. ↑ The use of memory map registers was carried forward to the 32-bit Sigma computers.
  2. ↑ Physically the memory map is contained in two 24-bit registers RL1 and RL2, each of which is set and cleared as a unit.

References

  1. 1 2 Calkins, Keith. "The COMPUTER That Will Not Die: The SDS SIGMA 7". Retrieved Nov 7, 2015.
  2. ↑ American Nuclear Society (1965). "<none>". Nuclear News (vol 8). Retrieved Nov 10, 2015.
  3. 1 2 "Eight Years Ago: May 29, 1968". Computerworld. May 31, 1976. Retrieved Nov 10, 2015.
  4. ↑ Xerox Data Systems (October 1969). Reference Manual XDS 940 Computer (PDF). Retrieved Nov 12, 2015.
  5. ↑ Scientific Data Systems (Nov 1964). SDS Monarch Reference Manual 900 Series Computers (PDF). Retrieved Dec 27, 2015.
  6. ↑ Scientific Data Systems (Dec 1969). MONARCH Reference Manual for 900 Series/9300 Computers (PDF). Retrieved Dec 30, 2015.

External links

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