Rajeev Alur

Rajeev Alur is Zisman Family Professor in the Department of Computer and Information Science at the University of Pennsylvania, United States.

Alur obtained his bachelor's degree in computer science from the Indian Institute of Technology at Kanpur, India, in 1987, and PhD in computer science from Stanford University, California, USA, in 1991. Before joining the University of Pennsylvania in 1997, he was with the Computing Science Research Center at Bell Laboratories. Alur's research spans formal modeling and analysis of reactive systems, hybrid systems, model checking, software verification, and design automation for embedded software. His contributions include timed automata and temporal specifications based on languages of nested words and trees. He is a Fellow of the ACM,^[1] a Fellow of the IEEE, and recently served as the chair of ACM SIGBED (Special Interest Group on Embedded Systems).

Awards and honors

President of India's Gold Medal for academic excellence.
A CAREER award of the US National Science Foundation.
CAV (Computer Aided Veriﬁcation) Award for fundamental contributions to the theory of real-time systems veriﬁcation, 2008 (with David Dill).
LICS (IEEE Symposium on Logic in Computer Science) Test-of-Time award^[2] for LICS 1990 paper “Model checking for real-time systems,” 2010 (with David Dill and Costas Courcoubetis).

References

↑ "Rajeev Alur". ACM Fellows. ACM. 2007. Retrieved 2010-01-23. For contributions to the specification and verification of reactive and hybrid systems.
↑ "LICS Test-of-Time award". For the pioneer work in the model checking of real-time systems.

External links

Wikimedia Commons has media related to Rajeev Alur.

Rajeev Alur homepage
Rajeev Alur at DBLP Bibliography Server
Rajeev Alur's publications indexed by Google Scholar

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