Junctionless nanowire transistor

Junctionless nanowire transistor (JNT), developed at Tyndall National Institute in Ireland, is a nanowire-based transistor that has no gate junction.[1] (Even MOSFET has a gate junction, although its gate is electrically insulated from the controlled region.) Junctions are difficult to fabricate, and, because they are a significant source of current leakage, they waste significant power and heat. Eliminating them held the promise of cheaper and denser microchips. The JNT uses a simple nanowire of silicon surrounded by an electrically isolated "wedding ring" that acts to gate the flow of electrons through the wire. This method has been described as akin to squeezing a garden hose to gate the flow of water through the hose. The nanowire is heavily n-doped, making it an excellent conductor. Crucially the gate, comprising silicon, is heavily p-doped; and its presence depletes the underlying silicon nanowire thereby preventing carrier flow past the gate.

Thus the device is turned off not by reverse bias voltage applied to the gate, as in the case of conventional MOSFET but by full depletion of the channel. This depletion is caused due to work-function difference (Contact_potentials) between the gate material and doped silicon in the nanowire.

This combination of n-doped nanowire and the p-doped channel forms a p–n junction and depletion layer is formed. Due to heavy concentration of the dopant atom in both nanowire and gate the depletion region is so large that virtually no carriers are present to conduct the current.

When a forward bias voltage is applied the thickness of the depletion region is reduced and gradually the channel forms which causes the current to flow again.

The JNT uses bulk conduction instead of surface channel conduction. The current drive is controlled by doping concentration and not by gate capacitance.[2]

Germanium has been used instead of silicon nanowires.[3]

References

  1. ↑ Kranti, A.; Yan, R.; Lee, C. -W.; Ferain, I.; Yu, R.; Dehdashti Akhavan, N.; Razavi, P.; Colinge, J. P. (2010). "Junctionless nanowire transistor (JNT): Properties and design guidelines". 2010 Proceedings of the European Solid State Device Research Conference. p. 357. doi:10.1109/ESSDERC.2010.5618216. ISBN 978-1-4244-6658-0.
  2. ↑ Colinge, J. P.; Kranti, A.; Yan, R.; Lee, C. W.; Ferain, I.; Yu, R.; Dehdashti Akhavan, N.; Razavi, P. (2011). "Junctionless Nanowire Transistor (JNT): Properties and design guidelines". Solid-State Electronics. 65-66: 33. doi:10.1016/j.sse.2011.06.004.
  3. ↑ Junctionless nanowire transistor fabricated with high mobility Ge channel. Yu 2013

Junctionless Nanowire Transistor: Properties and Device Guidelines

Ferain Junctionless Transistors (pdf)


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