Multiple patterning

Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the upcoming 10 nm and 7 nm node semiconductor processes and beyond. The premise is that a single lithographic exposure may not be enough to provide sufficient resolution. Hence additional exposures would be needed, or else positioning patterns using etched feature sidewalls (using spacers) would be necessary.

Coloring for multiple patterning. Multiple colors are needed to indicate different stages (e.g., first spacer, second spacer, trim, etc.) in the multiple patterning process flow.

Although EUV has been projected to be the next-generation lithography of choice, it would still require more than one lithographic exposure, due to the foreseen need to first print a series of lines and then cut them.[1] It is also likely more than one cut would be needed, even for EUV.[2]

Even for electron beam lithography, single exposure appears insufficient at ~10 nm half-pitch, hence requiring double patterning.[3][4]

Pitch Splitting

LELELE pitch splitting. Each feature color represents one group of features which may be imaged at once and patterned by a standard litho-etch procedure.

The earliest form of multiple patterning involved simply dividing a pattern into two or three parts, each of which may be processed conventionally, with the entire pattern combined at the end in the final layer. This is sometimes called pitch splitting, since two features separated by one pitch cannot be imaged, so only skipped features can be imaged at once. It is also named more directly as "LELE" (Litho-Etch-Litho-Etch). This approach has been used for the 20 nm and 14 nm nodes. The additional cost of extra exposures was tolerated since only a few critical layers would need them. A more serious concern was the effect of feature-to-feature positioning errors (overlay). Consequently, the self-aligned sidewall imaging approach (described below) has succeeded this approach.

Double Expose, Double Etch (trenches): Photoresist coating over first pattern; etching adjacent to previous features; mask removal

A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography .

This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration.[5]

A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.

A variation on this approach which eliminates the first hardmask etch is resist freezing, which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method, where the freezing is accomplished by surface hardening of the first resist layer.

Sidewall Image Transfer

Spacer mask: first pattern; deposition; spacer formation by etching; first pattern removal; etching with spacer mask; final pattern
SADP based on two successive depositions.

In spacer patterning, a spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. This is commonly referred to as Self-Aligned Doubled Patterning (SADP). The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.

As pitch splitting has become more difficult due to possible differences in feature positions between different exposed parts, sidewall image transfer (SIT) has become more recognized as the necessary approach. The SIT approach typically requires a spacer layer to be formed on an etched feature's sidewall. If this spacer corresponds to a conducting feature, then ultimately it must be cut at no less than two locations to separate the feature into two or more conducting lines as typically expected. On the other hand, if the spacer corresponds to a dielectric feature, cutting would not be necessary. The prediction of how many cuts would be needed for advanced logic patterns has been a large technical challenge. Many approaches for spacer patterning have been published (some listed below), all targeting the improved management (and reduction) of the cuts.


As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.[6]

The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other.[7] Any misalignment of masks or excursion in pre-patterned feature critical dimension (CD) will cause the pitch between features to alternate, a phenomenon known as pitch walking.[8]

The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.

Self-aligned contact/via patterning

Self-aligned via dual-damascene patterning.

Self-aligned contact and via patterning is an established method for patterning multiple contacts or vias from a single lithographic feature. It makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique is used in DRAM cells[9] and has been extended to patterning of active areas (more discussion below under "Industrial adoption"). It is also used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias.[10]

Spacer-is-Dielectric (SID) SADP

SID SADP for 2z nm metal half-pitch. 2D interconnecting patterns may be achieved without multiple block/cut masks, when the spacer (white) surrounds metal features.

In self-aligned double patterning (SADP), the number of cut/block masks may be reduced or even eliminated in dense patches when the spacer is used to directly pattern inter-metal dielectric instead of metal features.[11][12] The reason is the cut/block locations in the core/mandrel features are already patterned in the first mask.

Beyond 193 nm immersion SADP

There have been numerous concerns that multiple patterning diminishes or even reverses the node-to-node cost reduction expected with Moore's Law. EUV is more expensive than three 193i exposures (i.e., LELELE), considering the throughput.[13] Moreover, EUV is more liable to print smaller mask defects not resolvable by 193i.[14]

Self-Aligned Triple Patterning (SATP)

Self-aligned triple patterning has been considered as a promising successor to SADP, due to its introduction of a second spacer offering additional 2D patterning flexibility and higher density.[15] A total of two masks (mandrel and trim) is sufficient for this approach.[16] The only added cost relative to SADP is that of depositing and etching the second spacer. The main disadvantage of SATP succeeding SADP is that it would only be usable for one node. For this reason, self-aligned quadruple patterning (SAQP) is more often considered.

Protrusion Spacer Cutting

Spacer cutting by line protrusions. A way to cut spacers without extra masks makes use of protrusions in the mandrel itself.
SAQP grid routing enabled by protrusion cutting. 2D interconnect patterns can be patterned more efficiently by SAQP when grid routing is used, in conjunction with designed mandrel shapes. The grid is shown here for clarity of the routing scheme.

Mandrel or spacer core patterns can be designed to cut their own spacer patterns. A pair of opposing line protrusions can effectively squeeze out any feature in between if a spacer with a thickness exceeding half the distance between the protrusions is deposited, followed by the feature deposition.[17] This is ideal for use in SID SADP schemes. A similar approach is the use of linked features, i.e., narrow constrictions which separate features in spacer patterning without cutting.[18]

The protrusion cutting technique helps reduce the amount of cutting that is needed, and also enables the grid routing method described by Toshiba.[11][12][19] The number of masks used is the same as for SADP (1 mandrel/core, 1 trim/cut/block), since only pitch-doubled patterns need cutting. The remaining patterns do not need cutting or trimming, since they are patterned through the same initial exposure.

Reducing SAQP cuts by linking features. Linking features are narrow constrictions, which can also be used in spacer patterning to separate features without the use of cutting masks.

A similar approach to protrusion cutting is the concept of the linking feature.[20] The linking feature is a narrow constriction which separates features when the sidewall spacer is deposited and patterned. Line jogs, possibly track changing, are necessary to establish the linking feature.

EUV vs. Multiple Patterning

Beyond 18 nm half-pitch, with no pellicle for EUV in its current state,[21] a cost-reduced SATP or SAQP is expected to be put in place; SAQP is already in use for NAND flash. SAQP is also able to be used from 18 to 12 nm half-pitch, while EUV cannot address the 12 nm half-pitch.

At the 2016 EUVL Workshop, ASML reported that the 0.33 NA NXE EUV tools would not be capable of standard single exposure patterning for the 11-13 nm half-pitch expected at the 5 nm node.[22] A higher NA of 0.55 would allow single exposure EUV patterning of fields which are half the 26 mm x 33 mm standard field size.[22] However, some products, such as NVIDIA's Pascal Tesla P100,[23] will be bisected by the half-field size, and therefore require stitching of two separate exposures.[24] In any case, two half-field scans consume twice as much acceleration/deceleration overhead as a single full-field scan.[22][25]

The existing 0.33 NA EUV tools are challenged below 16 nm half-pitch resolution,[26] hence more than a single EUV exposure would be needed at a minimum for the 7nm and 5nm nodes.

The use of EUV for cutting exposures is also problematic for feature sizes relevant to 7nm node and below, as such features are also aggravated by the shot noise issue.[27]

Directed Self-Assembly

The number of masks may be reduced with the use of directed self-assembly (DSA) due to the provision of gridded cuts all at once within a printed area, which can then be selected with a final exposure.[28][29] Alternatively, the cut pattern itself may be generated as a DSA step.[30]

Much progress had been reported on the use of PMMA-PS block copolymers to define sub-20 nm patterns by means of self-assembly, guided by surface topography (graphoepitaxy) and/or surface chemical patterning (chemoepitaxy).[31] The key benefit is the relatively simple processing, compared to multiple exposures or multiple depositions and etching. The main drawback of this technique is the relatively limited range of feature sizes and duty cycles for a given process formulation. Typical applications have been regular lines and spaces as well as arrays of closely packed holes or cylinders.[32] However, random, aperiodic patterns may also be generated using carefully defined guiding patterns.[33]

The line edge roughness in block copolymer patterns is strongly dependent on the interface tension between the two phases, which in turn, depends on the Flory "chi" (χ) parameter.[34] A higher value of χ is preferred for reduced roughness; the interfacial width between domains is equal to 2a(6χ)−1/2, where a is the statistical polymer chain length.[35] Moreover, χN>>10 is required for sufficient phase segregation, where N is the degree of polymerization (number of monomer repeats in the chain). On the other hand, the half-pitch is equal to 2(3/π2)1/3aN2/3χ1/6. The fluctuations of the pattern widths are actually only weakly (square root) dependent on the logarithm of the half-pitch, so they become more significant relative to smaller half-pitches.

Specific Implementations for Contact/Via Patterns

Merged hole separation by etch shrink

Tokyo Electron Ltd (TEL) was able to resolve two merged contact holes by applying an etch shrink.[36] 31-32 nm contact half-pitch was achieved through this method.[37]

2D SID Spacer Patterning

The use of SID may be applied to 2D arrays, by iteratively adding features equidistant from the previously present features, doubling the density with each iteration.[38]

Triangular Spacer (Honeycomb Structure) Patterning

Samsung recently demonstrated DRAM patterning using a honeycomb structure (HCS) suitable for 20 nm and beyond.[39] Each iteration of spacer patterning triples the density, effectively reducing 2D pitch by a factor of sqrt(3).

Industrial adoption

Benefits of cut relocation. Left: Fewer connections with more difficult, diagonally placed cuts. Right: Cut relocation to align cuts also allows more connections.
SADP cut relocation. Relocation of SADP cuts on long lines can help reduce extra masks.
SAQP cut relocation. Just as for SADP, SAQP also benefits from cut relocation to reduce extra masks. Cut positions can be placed to reduce masks and optimize cut quality without density penalty in some cases.
Crossed spacer patterning for DRAM active area.

Memory patterns are already patterned by quadruple patterning for NAND[40] and crossed quadruple/double patterning for DRAM.[41] These patterning techniques are self-aligned and do not require custom cutting or trim masks.

Current EUV throughput is still more than 3x slower than 193 nm immersion lithography, thus allowing the latter to be extended by multiple patterning. Furthermore, the lack of an EUV pellicle is also prohibitive.

As of 2016, Intel is using SADP for its 10 nm node.[42] Intel is using triple patterning for some critical layers at its 14nm node,[43] which is the LELELE approach.[44] Triple patterning is already demonstrated in 10nm tapeout.[45] TSMC is deploying 7 nm in 2017 with multiple patterning.[46] Beyond the 5nm node, multiple patterning, even with EUV assistance, would be economically challenging, since the departure from EUV single exposure would drive up the cost even higher. However, at least down to 12 nm half-pitch, LELE followed by SADP (SID) appears to be a promising approach, using only two masks, and also using the most mature double patterning techniques, LELE and SADP.[47]

Patterning Costs

Patterning Method Normalized Wafer Cost
193i SE 1
193i LELE 2.5
193i LELELE 3.5
193i SADP 2
193i SAQP 3
EUV SE 4
EUV SADP 6

Ref.: A. Raley et al., Proc. SPIE 9782, 97820F (2016).

Compared to 193i SADP, EUV SADP cost is dominated by the EUV tool exposure, while the 193i SAQP cost difference is from the added depositions and etches. The processing cost and yield loss at a lithographic tool is expected to be highest in the whole integrated process flow due to the need to move the wafer to specific locations at high speed. EUV further suffers from the shot noise limit, which forces the dose to increase going for successive nodes.[48] On the other hand, depositions and etches process entire wafers at once, without the need for wafer stage motion in the process chamber. In fact, multiple layers may be added under the resist layer for anti-reflection or etch hard-mask purposes, just for conventional single exposure.

2D Multi-Patterning Options

Cutting lines to form irregular patterns uses the maximum number of masks. 2D patterning is generally preferred, but requires sufficient exposed feature pitch, followed by sufficient splitting or division of the pitch. On the other hand, LELE, LELELE, and SADP (SID) can avoid line cuts, while SATP or SAQP with grid routing can minimize line cuts. EUV 2D patterning is limited to >32 nm pitch.[26] For 16-18 nm half-pitch, the horizontal-vertical bias is over 3 nm, close to a node difference.[49][50] Consequently, EUV would require double patterning for its introduction at 7nm node below 20 nm half-pitch;[51] this may prove too costly to implement against the already established LELELE triple patterning, or the immersion-based combination of mature double patterning techniques LELE+SADP [47] or the implementation of SAQP, which is twice applied SADP, especially the SID form of SADP,[11] with LELE and SID SADP already established for 32 nm and 24 nm half-pitch, respectively.

Half-pitch Technique
32 nm LELE[52] (128 nm pitch lithography)
24 nm LELELE (144 nm pitch lithography) or SADP (SID)[11] (mandrel pitch = 96 nm)
19 nm LELELE (114 nm pitch lithography) or SADP (SID) (mandrel pitch = 76 nm) + 1 cut if grating no protrusion[17]
15 nm LELELE (90 nm pitch lithography) or LELE (120 nm pitch lithography) + SADP (SID) or SAQP (mandrel pitch = 120 nm) + cut/trim (Note: EUV requires LELE double patterning)[22]
12 nm LELE (96 nm pitch lithography) + SADP (SID) or SAQP (mandrel pitch = 96 nm) + cut/trim (Note: EUV requires LELELE triple patterning)[22]

Notes: SE=Single Exposure (conventional lithography); LELE=Litho-(followed by)Etch 2 times; LELELE=Litho-(followed by)Etch 3 times;SADP=Self-Aligned (Spacer) Double Patterning; SID = Spacer-Is-Dielectric

From a lithographic quality point of view, pitch quartering with 193 nm immersion is better than EUV single exposure. For example, 18 nm half-pitch with 0.33 NA EUV has k1=0.44, while 4x18=72 nm half-pitch with 1.35 NA immersion gives k1=0.50. The ~14% advantage is always maintained across target pitch. The difficulty increases faster as k1 drops below 0.35. On the other hand, multiple passes would present another difficulty for quadruple patterning. Properly shaping the mandrel is not trivial.[53] Long lines running in one direction require the most cuts; a cut exposure and mask is needed for every path turn. In contrast, spacer patterns with path turns already included do not require cutting if they are used for encapsulating metal.[11]

Mask Costs

The mask cost strongly benefits from the use of multiple patterning. The EUV single exposure mask has smaller features which take much longer to write than the immersion mask. Even though mask features are 4x larger than wafer features, the number of shots is exponentially increased for much smaller features. Furthermore, the sub-100 nm features on the mask are also much harder to pattern, with absorber heights ~70 nm.[54]

SADP Library Patterns. Predefined constructs for SADP may be available from EDA companies to systematize the SADP flow, including core/mandrel placement (red), cut placement (orange), and spacer location (green).

Multiple Patterning Specific Issues

Issue LELE LELELE SID SADP SAQP
Overlay between 1st and 2nd exposures, especially where stitching among all three exposures, especially where stitiching N/A (no cut needed) between core and cut exposures
Exposed feature width (1) 1st exposure (2) 2nd exposure (1) 1st exposure (2) 2nd exposure (3) 3rd exposure core feature (1) core feature (2) cut shape
Feature slimming target width 1/4 exposure pitch 1/6 exposure pitch 1/4 core pitch 1/8 core pitch
Spacer width N/A N/A 1 spacer (1) 1st spacer (2) 2nd spacer

Multiple patterning entails the use of many processing steps to form a patterned layer, where conventionally only one lithographic exposure, one deposition sequence and one etch sequence would be sufficient. Consequently, there are more sources of variations and possible yield loss in multiple patterning. Where more than one exposure is involved, e.g., LELE or cut exposures for SAQP, the alignment between the exposures must be sufficiently tight. Current overlay capabilities are ~0.6 nm for exposures of equal density (e.g., LELE) and ~2.0 nm for dense lines vs. cuts/vias (e.g., SADP or SAQP) on dedicated or matched tools.[55] In addition, each exposure must still meet specified width targets. Where spacers are involved, the width of the spacer is dependent on the initial deposition as well as the subsequent etching duration. Where more than one spacer is involved, each spacer may introduce its own width variation.

Mainstream Use in NAND Flash

Multiple patterning is routinely used for NAND Flash memory manufacturing. 14 nm is the smallest dimension achieved in 2016.[56] 3D NAND Flash also includes SADP.[57]

Another cost perspective comes from comparing patterning with multiple spacers vs. 3D NAND Flash fabrication, which requires at least 64 distinct layer depositions and etches of those same layers.[58] 16 nm planar NAND requires SAQP (2x SADP) and is the cheapest memory product offered in 2016.[59]

10nm FinFETs

Samsung announced mass production of 10nm FinFETs in October 2016, featuring triple patterning.[60] Samsung also has developed self-aligned triple patterning (US Patent 9412604).

7nm and 5nm FinFETs

Self-aligned quadruple patterning is already the established process to be used for patterning fins for 7nm and 5nm FinFETs.[61] With SAQP, each patterning step gives a critical dimension uniformity (CDU) value in the sub-nanometer range (3 sigma).

References

  1. ↑ E. van Setten et al., Proc. SPIE 9661, 96610G (2015).
  2. ↑ http://www.eetimes.com/document.asp?doc_id=1327919 EUV 5nm test
  3. ↑ Double patterning HSQ processes of zone plates for 10 nm diffraction limited performance
  4. ↑ H. Duan, et al., JVST B8, c6c58 (2010).
  5. ↑ IMEC double patterning
  6. ↑ X. Hua et al., J. Vac. Sci. Tech. B, vol. 24, pp. 1850-1858 (2006).
  7. ↑ Y-K Choi et al., J. Phys. Chem. B, vol. 107, pp. 3340-3343 (2003).
  8. ↑ Chao, Robin; Kohli, Kriti K.; Zhang, Yunlin; Madan, Anita; Muthinti, Gangadhara Raja; Hong, Augustin J.; Conklin, David; Holt, Judson; Bailey, Todd C. (2014-01-01). "Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs". Journal of Micro/Nanolithography, MEMS, and MOEMS. 13 (4): 041411–041411. doi:10.1117/1.JMM.13.4.041411. ISSN 1932-5150.
  9. ↑ US Patent 6165880, assigned to TSMC.
  10. ↑ Y. Loquet et al., Microelec. Eng. 107, 138 (2013).
  11. 1 2 3 4 5 C. Kodama et al., IEEE Trans. CAD Integ. Circ. and Sys., vol. 34, 753 (2015).
  12. 1 2 US Patent Application 20150021782, assigned to Kabushiki Kaisha Toshiba.
  13. ↑ D. Civay et al., J. Micro/Nanolith. MEMS MOEMS 14, 023501 (2015).
  14. ↑ K. Seki et al., Proc. SPIE 9658, 96580G (2015).
  15. ↑ Y. Chen et al., Proc. SPIE 7973, 79731P (2011).
  16. ↑ M. Mirsaeedi et al., IEEE Trans. VLSI Syst. 22, 1170 (2014).
  17. 1 2 US Patent 8697538, assigned to Winbond.
  18. ↑ US 20160181110, assigned to TSMC.
  19. ↑ K. Nakayama et al., Proc. SPIE 8327, 83270V (2012).
  20. ↑ U.S. Patent Application 20160181110, assigned to TSMC.
  21. ↑ EUVL 2016 Workshop update
  22. 1 2 3 4 5 ASML High-NA EUV
  23. ↑ NVIDIA Pascal Tesla P100 Unveiled - 15.3 Billion Transistors on a 610mm2 16nm Die
  24. ↑ Microlithography: Science and Technology, 2nd ed., B. W. Smith and K. Suzuki (eds.), CRC Press, 2007, p. 94.
  25. ↑ Handbook of Semiconductor Manufacturing Technology, Y. Nishi and R. Doering (eds.), CRC Press, 2000, p. 475.
  26. 1 2 T-B. Chiou et al., Proc. SPIE 9781, 978107 (2016).
  27. ↑ EUV shot noise at 7nm node
  28. ↑ Synopsis Presentation at Semicon West 2013
  29. ↑ M. C. Smayling et al., Proc. SPIE 8683, 868305 (2013).
  30. ↑ Z. Xiao et al., Proc. SPIE 8880, 888017-3 (2013).
  31. ↑ S. H. Park et al., Soft Matter, 6, 120-125 (2010).
  32. ↑ C. G. Hardy and C. Tang, J. Polymer Sci. Pt. B: Polymer Phys., vol. 51, pp. 2-15 (2013).
  33. ↑ L-W. Chang et al.IEDM 2010 Technical Digest, 752-755 (2010).
  34. ↑ NIST 2011 report on LER in PS-b-PMMA DSA
  35. ↑ A. N. Semenov, Macromolecules 26, 6617 (1993).
  36. ↑ K. Oyama et al., Proc. SPIE 9051, 90510V (2014).
  37. ↑ M. C. Smayling et al., Proc. SPIE 9426, 94261U (2015).
  38. ↑ B. Mebarki et al., U. S. Patent 8,084,310, assigned to Applied Materials.
  39. ↑ J. M. Park et al., IEDM 2015, 676 (2015).
  40. ↑ Hynix M1X NAND
  41. ↑ U.S. Patent 9318369, assigned to Samsung.
  42. ↑ Intel discusses 10nm
  43. ↑ Intel goes to 7nm without EUV
  44. ↑
  45. ↑ Triple patterning is becoming common at 10nm
  46. ↑
  47. 1 2 F. T. Chen et al., Proc. SPIE 8683, 868311 (2013).
  48. ↑ F. T. Chen et al., Proc. of SPIE vol. 8326, 82362L (2012).
  49. ↑ S. Hong et al., Proc. SPIE 8679, 867928 (2013).
  50. ↑ G-J. Kim et al., J. Micro/Nanolith. MEMS MOEMS 15, 023503 (2016).
  51. ↑ ASML 7nm EUV slide 46
  52. ↑ H. Tomizawa et al., IITC 2011.
  53. ↑ B. J. Lin, Microel. Eng. 143, 91 (2015).
  54. ↑ R. R. Haque et al., Proc. SPIE 9776, 97760F (2016).
  55. ↑ Extending immersion lithography to 1xnm nodes
  56. ↑ 14 nm NAND Flash from Samsung in 2016
  57. ↑ Samsung 48L 3D NAND
  58. ↑ 3D NAND process challenges
  59. ↑ Return to planar NAND
  60. ↑ Samsung announced triple patterning 10nm
  61. ↑ SAQP for FinFETs
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